The present invention concerns testing electronic-circuit boards and in particular detecting open circuits between component pins and the board tracks to which they should be electrically connected.
Testing for proper functioning of electronic-circuit boards has now been performed automatically for decades, and for most of that time various test techniques have been used to detect open circuits between component pins and the board tracks to which they should be soldered or otherwise electrically connected. For much of the history of board testing, however, such open circuits have been a relatively minor concern. They occurred relatively infrequently, so manual probing to diagnose them was acceptable in most situations.
We refer here to "manual" probing because most high-volume tests are performed in a more-automatic manner. Typically, the board is placed in a "bed of nails" fixture, in which a large number of spring probes, or "nails," simultaneously contact respective nodes on the bottom of the board to be tested, and a user does not have to position those probes manually. Various automatic switching mechanisms in an automatic circuit tester then connect the nails to various driving and sensing circuitry, causing stimulus to be applied to the board and its response to be recorded.
In the past, this approach was not typically used to detect open pins because the nails typically contact the "bottom," or non-component side, of the usual, "one-sided" circuit board, while the most-straight-forward way of testing for the proper pin connection involves placing a probe on the component pin, which is on the other side of the board, to determine whether a signal applied to the board track appears on the pin.
But open pins have recently become a problem of greater significance. The reason for this largely is that pin pitches have become increasingly fine, and this has made it harder to register the pin accurately with its proper location on the board. Tester manufacturers therefore began to put some effort recently into providing more-automatic means of testing for open component pins. Obviously, the best approach would be one that can be performed through the bed of nails exclusively, without the additional fixturing complexity that affording physical access to the board's component side necessitates. Automatic-type access to the component side of the board typically necessitates the use of so-called clamshell fixtures, which employ two arrays of probes, one for each face of the circuit board. Such an arrangement exacts penalties in fixture cost and throughput, and it is a large part of the reason why manufacturers have traditionally favored one-sided boards: they could be tested without clamshell fixtures.
Efforts at developing open-pin tests therefore initially concentrated on approaches that required only a single, bed-of-nails probe array, and some approaches have been developed that can detect open pins in a wide range of situations without resorting to clamshell fixtures. But there are certain limited test situations that thus far have not proved amenable to one-sided open-circuit testing. These are usually situations in which the tester's instrument complement is rather limited and/or the board employs components, such as custom ASICs, for which adequate diagnostic information is not available. Because an early solution to the problem of finding one-sided tests for open circuits in these situations began to appear unlikely, tester manufacturers eventually concluded that they needed to provide tests that resort to clamshell fixtures. It is to tests of this sort that the invention described below is directed.
Probing considerations on the component side of the board differ from those that prevail on the non-component side. As a probe target, for instance, a component pin is much more fragile and sometimes more difficult to hit. Moreover, it is virtually impossible to make actual contact with a pin of a surface-mount-technology (SMT) component. So component-side probes proposed for high-volume open-circuit tests have usually been of the non-contact type and typically capacitive.
In a typical test that employs a capacitive probe, the stimulus signal is applied (typically from the non-component side) to a track to which the component pin in question should be connected. Of course, the pin is mounted in a component package that houses an integrated circuit, and the internal connection between the pin and the integrated circuit is often provided by a lead frame. The lead frame provides a conductive surface that can capacitively couple the pin signal to a capacitive probe in the form of a conductive plate placed adjacent to the component package's upper surface.
Now, to determine whether the connection is made properly, the capacitive open-circuit-testing technique essentially measures the series capacitance in the path from the board track through the pin and the lead frame to the capacitive probe. If there is a connection between the track and the pin, that capacitance consists essentially of the capacitance between the capacitive probe and the lead-frame leg connected to the pin being tested. But an improper connection interposes a further, much smaller capacitance between the component pin and the track to which it should be connected. This results in a very low series capacitance and thus a very high impedance, which greatly attenuates the signal coupled from the path to the probe. This absence of a significant signal can therefore be taken as an indication of an open pin.
While the foregoing description of a capacitive test describes the manner in which it should ideally work, complications arise in practice. Board topology can result in capacitances that parallel the connection-dependent capacitance of interest and thus result in significant measured capacitance even when the pin is open. And setting a threshold to accommodate such connection-independent values is complicated by the fact that the capacitance that indicates proper connection for one pin may not be such an indication for another pin. Indeed, there are often differences even for corresponding pins of the same type of board component mounted in different locations on a board. A result of this fact is that capacitive testing is not particularly reliable if the same threshold level is used as the criterion for determining the proper connection of every pin; using a high level uniformly tends to result in an unnecessarily high frequency of false open-circuit indications, while using a low level uniformly tends to allow too many open circuits to pass undetected.
To increase reliability, a tester will typically be subjected to "training." In training, capacitance measurements are made for the various pins of a known good board of the type to be tested. The values thus measured are stored and employed in imposing the criteria by which connection integrity is judged. Specifically, if the capacitance measured for a given pin on a known good board has a given value, then the corresponding pin on a board under test is judged not to be connected properly if the measured capacitance is less than, say, a predetermined percentage of the capacitance measured for that pin on the known good board. By thus employing training in connection with the testing process, the reliability of the testing process is considerably increased.